Dielectric Resonator Oscillators

Dielectric Resonator Oscillators (DRO) are used widely in today's electronic warfare, missile, radar and communication systems. They find use both in military and commercial applications. The DROs are characterized by low phase noise, compact size, frequency stability with temperature, ease of integration with other hybrid MIC circuitries, simple construction and the ability to withstand harsh environments.

These characteristics make DROs a natural choice both for fundamental oscillators and as the sources for oscillators that are phase-locked to reference frequencies, such as crystal oscillators.

This paper summarizes design techniques for DROs and the voltage- tuning DRO (VT-DRO), and presents measured data for them including phase noise, frequency stability and pulsing characteristics.

Design Techniques

The design technique we will discuss is for a dielectric resonator (DR) to be used as a series feedback element. Practically, a GaAs FET or a Si-bipolar transistor is chosen as the active device for the oscillator portion of the DRO circuit. The Si-bipolar transistor is generally selected for lower phase noise characteristics, while the GaAs FET is required for higher frequencies.

For example, a DRO with a DR as a series feedback element can be designed using following design procedure:

1. Select an active device that is capable of oscillation at the design frequency, and use the small signal S-parameter of the device for the design.

2. Add a feedback circuit to ensure that the stability factor of the active device with the feedback circuit is less than unity with enough margin.

3. Create an active one-port analysis that consists of the active device, the feedback circuit, the matching network and the load as shown as figure1. Optimize Za (?) with the parameters in the feedback circuit and in the matching network to ensure that Ra (?0) is less than or equal to -25 ohms and Xa (?) has the possible maximum variation near resonance in order to insure high circuit Q.

Figure 1. Schematic diagram of the series feedback DRO

Determine the electrical spacing of the dielectric resonator such that the reactance it presents to the base or gate of the transistor is the negative of Za. The characteristic impedance of the output transmission line, Zg, is usually selected to be 50 ohms.

The open stub (characteristic impedance of 50 ohms), which is terminated at the source end of the FET, serves as the feedback element. By adjusting the electric length of the feedback stub, various port impedance characteristics for Za (?) in the band of interest (6-15 GHz) can be obtained.

From the port reactance characteristic, we observe that the shorter the electric length of feedback stub, the more rapid the port reactance change with frequency. On the other hand, for the active port, a shorter feedback stub induces higher negative resistance.

Finally, negative resistance is reduced if the electrical length of the feedback stub is less than 25 degrees. Taking etch tolerances into consideration, the length of the feedback stub is chosen as 45 degrees.

10 GHz Example:

The resultant input impedance of the active port is Za = -40.8 -j62.5 ohms at the desired frequency. The negative resistance of -40.8 ohms is sufficient to allow the transistor to build up and sustain oscillation at the desired frequency.

It remains to determine the length of a 50 ohm terminated microstrip line between the coupling plane of the DR and the gate terminal of the active device. We know that the load must have a reactance XI = 62.5 ohms to resonate with the reactance of the active device input (gate) port.

Looking toward the DR from this port, the circuit appears as if it were an open circuited transmission line stub for which the open circuit appears at the equivalent coupling plane of the DR, about equal to the location of the DR's centerline drawn perpendicular to the line to which it couples. Accordingly, its reactance is XI = Zg cot (?g), from which the spacing of the DR can be determined. In the present series feedback example, the computed electric length is 141.3 degrees at 10.4 GHz. A photograph of the 10.4 GHz DRO is shown in

Figure 2. Photograph of a 10GHz DRO.

Small signal S parameters are used in the design, whereas in reality the oscillator's voltage amplitudes increase until saturation, at which the DRO reaches its steady state output power. This saturation, by definition, corresponds to the high level S parameter case. Nevertheless, designs based upon the small signal behavior are found to yield a good first order solution, requiring minor adjustment for high level operation at the desired frequency.

The frequency stability of the DRO over temperature is selected by taking into account the total circuit. In other words, the temperature characteristics of the supporting structure, the epoxy with which the DR is attached, the RF device, and the circuit housing must be accounted for during selection of the dielectric resonator material and temperature coefficient.

A frequency stability of 3 parts per million per degree Centigrade (3 ppm/C°) for a DRO operating around 10 GHz is typically achievable. This corresponds to a frequency shift of 30 kHz per Centigrade degree shift.

Differences in DR Material

Besides temperature coefficient, the DR is selected for its size and dielectric constant. Figure 3 shows that the size of the DR (the thickness to diameter ratio of a DR is generally kept to 0.4 for the widest mode separation) is inversely proportional to the frequency of the DRO for the same dielectric material.

Figure 3. Picture of DRO of different diameters for close to the same freq.

On the other hand, Figure 4 shows that dielectric resonators of almost the same size but with different dielectric materials can be used for DROs of various frequencies. The 12 GHz DRO with integral amplifier shown has the smallest size (0.515" x 0.535" x 0.375") ever reported using hybrid MIC techniques, yet it delivers more than 20 dBm of output power at 105 C°.

Figure 4. DROs of different frequencies with different dielectric material used for the CRs

Electronic Frequency Tuning

Frequency tuning of a DRO can be achieved by using voltage controlled diodes (varactors). The circuit configuration for coupling the varactors to the DR consists of an additional line paralleling that which couples the DR to the active device, and placed on the opposite side of the DR see figure 5. In the example shown two varactors are attached to the ends of a microstrip half wavelength resonator having characteristic impedance Zt.

Figure 5a. Schematic of VT-DRO.

At the DR plane of coupling, the transmission line can be treated as two quarter-wavelength impedance transformers (or, more precisely two impedance inverters) terminated with two tuning varactors. The varactors' capacitive variation at the end of the inverter is transformed into inductive variation at the plane of the coupling by the impedance inverter.

By increasing the coupling between the DR and the varactor/microstrip line, the tuning bandwidth of the DRO can also be increased. There is a trade-off for wider tuning bandwidth in that degraded phase noise and poorer frequency stability results, mainly due to the resultant equivalent degradation in the unloaded Q of the dielectric resonator.

Keeping this in mind, it is necessary that the electrical tuning band of the DRO be wider than the anticipated frequency drift of the oscillator versus temperature.

In summary, coupling the dielectric resonator to the tuning line and coupling the tuning circuit to the oscillator circuit must be kept in balance. Than can easily be done without significantly degrading the phase noise characteristics or temperature performance.

Temperature Compensation DROs

Electrical tuning of a DRO can be used to compensate for frequency drift over temperature. The DRO frequency change over temperature is measured for various temperatures to establish a frequency drift profile. A correction profile is calculated and a correction circuit consisting of thermistors (resistors that very with temperature) and resistors is calculated. This temperature sensor information is converted into proper tuning voltage and is fed into the tuning port of the DRO.

Figure 5b. Block diagram of Temperature Compensated DRO (TC-DRO).

This compensation technique is well known in TCXOs and the three or four typical compensation profiles are well established and easily fabricated.

The temperature compensated DROs using the analog approach exhibit + /- 0.3 ppm per degree C stability with DRO output frequencies up to 20 GHz from and over the temperature range -54 C to + 105 degrees C.

Figure 6. TC-DRO temperature profile.

The analog approach is smooth and continuous with no thermal toggling. The digital approach of temperature compensation also can provide similar frequency stability but much more complex circuitry is required.

Phase Locked Loop DROs

The VT-DRO can be used in conjunction with a sampling phase detector (SPD) to form the correction loop of a phase-locked source. The main advantage of PLL-DRO is its superior phase noise performance. Inside the loop, the phase noise has the characteristics of a frequency up-converted crystal oscillator [20log(N)] and outside the loop, the phase noise is the VT-DRO. The loop bandwidth can be shifted in frequency to minimize the loop circuit noise peaking.

Figure 7. Noise plot of PLL-DRO

The tuning sensitivity ratio (frequency change versus control voltage) is relatively consistently, which makes the loop circuit relatively consistent. The low phase noise and small circuit size make the VT DRO very attractive in phase-locked source applications.

Phase Noise

One of the important characteristics of a DRO is its phase noise at 10 kHz or higher away from the carrier. The phase noise of a DRO is dependent upon the active device used, the coupling of oscillation power to the DR, and the amount of power delivered to load. Figure 10 shows the typical phase noise characteristics of a DRO using Si-bipolar transistors and GaAs FETs. The Si-bipolar transistor provides about a 10 dB improvement in phase noise, which is generally believed to be contributed by Vfm noise of the GaAs FETs. Phase noise increases with the square of operating frequency, thus to obtain the phase noise level of a DRO at frequencies other than 10 GHz, add 20x log10 [f(GHz)/10] to the values shown in Figure 10. For example, corresponding phase noise will be 6 dB greater for a 20 GHz DRO.

As more energy is stored in the dielectric resonator, the temperature characteristic of the DRO more closely follows that of the DR, however more of the active device's power is dissipated in the DR, leaving less for output. Also the phase noise of the DRO also may degrade. Therefore, some compromise often must be made between the DRO's temperature stability and phase noise.

Pulsing Characteristics

For some applications it is desirable that the output power of the DRO be turned on and off, subjected to pulsing from TTL control signals. Pulsing circuitries can be placed at the drain (Figure 12a) or at the ground (Figure 12b). Both circuits yield similar pulsing rise time, defined as the time between 50% TTL input and 90% RF output. A rise time 600 nsec has been obtained for a 16 GHz DRO with 20 dBm output power and phase noise of 86 dBc/Hz at 10 kHz from the carrier. The high unloaded Q (Qu) nature of the DR requires longer time to build up the energy in the resonator compared a free running oscillator.

To increase the pulsing speed, relatively high loss dielectric resonator material can be used together with tighter coupling of the microstrip line to the DR, at the expense of reduced unloaded Q and significant impact on phase noise and frequency stability. While the frequency stability of a DRO can be compensated by using a DR of proper temperature characteristics, the phase noise appears to be the parameter that must be traded off for faster rise time pulsing. A similar design of a DRO at 16 GHz, when optimized for pulse rise time, exhibits less than 100 nsec rise time but a phase noise degraded to 73 dBc/Hz at 10 kHz from the carrier.

The settling time of the fast pulsing DRO is less than 100 nsec when the frequency is measured with 80 +1/ -100 kHz referenced to the frequency measured at 500 nsec and drift within +1/ -100 kHz from 500 nsec to 1 sec.

Fuente: http://www.gedlm.com/DRO/DRO.asp

Ver blogger original: http://nubia-anc.blogspot.com/

Materia: CRF

An Invisibility Cloak may be a Reality Soon

A Michigan Technological University scientist has worked on making an invisibility cloak, and who knows one day you might just be the owner of one!

Elena Semouchkina, an associate professor of electrical and computer engineering at Michigan Tech, has found ways to use magnetic resonance to capture rays of visible light and route them around objects, rendering those objects invisible to the human eye.

In a paper appearing in the journal Applied Physics Letters, Semouchkina and colleagues describe developing a nonmetallic cloak that uses identical glass resonators made of chalcogenide glass, a type of dielectric material (one that does not conduct electricity). In computer simulations, the cloak made objects hit by infrared waves - approximately one micron or one-millionth of a meter long - disappear from view.

Earlier attempts by other researchers used metal rings and wires. Semouchkina said: "Ours is the first to do the cloaking of cylindrical objects with glass."

Her invisibility cloak uses metamaterials, which are artificial materials having properties that do not exist in nature, made of tiny glass resonators arranged in a concentric pattern in the shape of a cylinder. The "spokes" of the concentric configuration produce the magnetic resonance required to bend light waves around an object, making it invisible.

Semouchkina and her team now are testing an invisibility cloak rescaled to work at mocrowave frequencies and made of ceramic resonators. They're using Michigan Tech's anechoic chamber, a cave-like compartment in an Electrical Energy Resources Center lab, lined with highly absorbent charcoal-gray foam cones.

Fuente: http://www.medindia.net/news/An-Invisibility-Cloak-may-be-a-Reality-Soon-71765-1.htm
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF

Hittite Microwave Corporation to Release Second Quarter

CHELMSFORD, Mass., Jul 01, 2010 (BUSINESS WIRE) -- Hittite Microwave Corporation /quotes/comstock/15*!hitt/quotes/nls/hitt (HITT 47.79, +0.83, +1.77%) plans to announce its financial results for the second quarter ended June 30, 2010 after the close of market on Thursday, July 22, 2010.

In conjunction with the release, Hittite Microwave will conduct a conference call at 5:00 p.m. ET on July 22, 2010, hosted by Mr. Stephen G. Daly, Chairman, President and Chief Executive Officer, and Mr. William W. Boecke, Vice President and Chief Financial Officer. A live webcast of the call will be available online on the Hittite Microwave website. To access the live webcast, go to the Investor page of the Hittite Microwave website at www.hittite.com and click on the webcast icon located under the News & Events section. Hittite Microwave encourages each visitor to review the site prior to the call to ensure that the visitor's computer is configured properly. A telephonic replay of the call also will be available for one week after the live call by dialing (303) 590-3030 access code 4325633. The webcast replay of the call will also be available after the live call by visiting the Investor page at www.hittite.com.

About Hittite Microwave Corporation

Hittite Microwave is an innovative designer and developer of high-performance integrated circuits, or ICs, modules, subsystems and instrumentation for technically demanding radio frequency, or RF, microwave and millimeterwave applications. Products include amplifiers, attenuators, broadband time delay, comparators, data converters, DC power conditioning, DC power management, dielectric resonator oscillators, filters-tunable, frequency dividers and detectors, frequency multipliers, high speed digital logic, interface, limiting amplifiers, mixers and converters, modulators and demodulators, mux/demux, oscillators, passives, phase lock loop (PLL), PLL with integrated VCOs, phase shifters, power detectors, sensors, switches, synthesizers, transimpedance amplifiers and variable gain amplifiers. Hittite's products are used in a variety of applications and end markets including automotive, broadband, cellular infrastructure, fiber optic, microwave and millimeterwave communications, military, space, and test and measurement. The company utilizes radio frequency integrated circuits (RFIC), monolithic microwave integrated circuits (MMIC), multi-chip modules (MCM) and microwave integrated circuit (MIC) technologies. The company is headquartered in Chelmsford, MA.

Fuente: http://www.marketwatch.com/story/hittite-microwave-corporation-to-release-second-quarter-2010-financial-results-on-july-22-2010-2010-07-01?reflink=MW_news_stmp
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF

EM simulation for EMC: keeping a lid on interference

Simulating your product’s EM (electromagnetic) radiation will help ensure that you pass FCC (Federal Communications Commission) and CE (Conformité Européenne) tests and will keep your project on schedule. Every product must have EMC (electromagnetic-compatibility) tests. The FCC requires that you test your products to ensure that EM radiation will not cause interference with radios, phones, and TVs. In addition to testing for EM radiation, your product must also exhibit electromagnetic immunity, meaning that a strike from a defined EM pulse will not significantly disturb the product’s performance (Reference 1).

You need sophisticated software tools to perform EM simulations. These simulations must take into account both small and large features over a broad frequency range (Figure 1). You must also select an appropriate simulation method, which can be either a timedomain technique, such as FEM (finite-element method), or a frequency-based one, such as MOM (method of moments). For the largest problems, you need to break the simulations into subdomains or use asymptotic-solutions techniques.

Once you have a powerful computer and the right software, you must place physical and electrical data into the software using database importation or by feeding in mechanical configurations with Gerber and DXF (Drawing Exchange Format) files and manually entering dielectric constants and board-stackup specifications. Finally, you must provide a stimulus to the software, either with Spice or S-parameter data or with a near-field-simulation result from a previous simulation on a subsystem in the product.

Spice versus field solver

You cannot use Spice to simulate EMC because Spice is a matrix-math computational solver for Kirchhoff’s equations that uses lumped-element models of discrete components. At best, you can use Spice to model a lossy transmission line to define what happens to the signal, but it does not reveal which fields radiate into space. For this problem, you need a field-solver simulation (Reference 2). A field solver uses finite elements, meshing, and iteration to solve Maxwell’s equations for your circuit design. EM-simulation software must account for the mechanical configuration and the materials you use in the design (see sidebar “Computer power”).

The highest frequencies you are trying to simulate and the size of the circuit dictate the scope of the field-solver problems you will encounter. Wavelengths are 30m at 10 MHz, meaning that a 1-cm trace is much smaller than the wavelength. The software would not have to mesh the trace into smaller sections to iterate toward a solution. The 30m wave acts almost uniformly on the 1-cm trace.

Imagine a 10-GHz radar signal with a 2-cm wavelength bouncing off a battleship. The field-solver software must break the battleship into billions of tiny meshes, fitting 10 or even 100 into each square centimeter of the ship’s surface. The surface of a metal battleship is not purely reflective, so the software must do 3-D meshing and has even more elements to compute because it must also do the interior areas. The workstation that runs the software needs hundreds of gigabytes of memory to store intermediate calculations for the meshes, and it would take months to solve for the fields over this large area. You can solve the memory problem by breaking the problem into domains and solving them iteratively, but that approach would take even longer.

When you test for EMC, small mechanical features result in big changes in performance. A slot in a cover, a misrouted trace, or an aluminum heat sink on an IC package can all cause your product to fail EMC-radiation testing. These mechanical features serve as antennas, so they also receive energy from their surroundings, giving your product poor electromagnetic immunity. The standards require compliance to frequencies of 960 MHz and beyond. For this reason, simulating for EMC is a broadband problem with heavy computational requirements. You must simulate for those frequencies; thus, simulating a large system takes an unacceptably long time. The complexity of the problem is monstrous even for a rather simple product. Also, multiple phenomena, including electrical fields radiating from traces, magnetic fields from inductors, and both types of fields radiating into and from cables, are responsible for EMI (electromagnetic interference).

A typical EM-simulation strategy divides the problem into pieces and depends on both relative and absolute measurements. You need to know how customers will use the product, divide your EMC analysis into manageable pieces, and then evaluate those pieces as they relate to the whole problem. The principle of superposition can be a big help. It states that, for all linear systems, the net response at a given place and time that two or more stimuli cause is the sum of the responses that each stimulus individually would have caused. If three main contributors are affecting your EMI signature, you can individually simulate each one, with different techniques if necessary, and then add the results in an rms (rootmean-square) fashion if they are not related. Sometimes, though, one system affects the other, and they do interact.

Once you have simulated the PCB (printed-circuit board), you represent that simulation as a radiating model that you then plug into a larger assembly. Even if you can use likely signals to simulate the radiation from your PCB, you may also have a few switching power supplies that have not only electric fields, but also magnetic ones. A case surrounds these components, and the cables from the product are antennas that radiate energy to make you fail EMC testing and receive energy to make your circuit fail immunity tests. You may also have to decide how disparate radiation patterns add up to a total emissions level. That decision may bring up the ugly reality of nonlinear circuits, such as RF-power amplifiers that you drive into saturation to get good efficiency. Superposition techniques don’t work in nonlinear systems and may cause you to underestimate the radiation from the circuitry.

Selecting a technique

The mathematicians and software wizards who work at field-solver companies have developed many methods to help you do EM simulations. You can use 2-D simulation programs, such as HyperLynx and SIwave (signal-integrity wave) to evaluate the EMC of a PCB. Fixing the signal- or power-integrity problems on the card often fixes your EMC problem, as well. You can use time-domain simulations for lower frequencies and smaller physical problems. The key benefit of the time-domain techniques is that they use GPU (graphics-processing-unit) cards, which speed up the math.

James Stack, training, applications, and consulting manager at Remcom Technology Solutions, reports that adding one GPU speeds solvers by a factor of 30 and stuffing your computer with four GPU cards can speed things up by a factor of 150. David Johns, vice president of technical support and engineering at CST (Computer Simulation Technology), reports that his company’s time-domain solver runs problems 12 times faster with a GPU.

Unfortunately, at higher frequencies, time-domain techniques are not the best way to solve for EM fields. FEM and time-domain field-solver techniques work best for slower signals, while MOM and asymptotic solvers work for faster speeds and larger problems. You are better off using a frequency-based solver in a PC workstation with lots of memory and multiple CPU cores. Companies such as Feko and CST use MLFMM (multilevel- fast-multipole-method) techniques, which solve large problems with less computer power. As the problems become large and must run at frequencies greater than 10 GHz, you must use special solvers that can do asymptotic analysis, which solves for large sets. In some simulations, one physical domain affects another (see sidebar “Multiphysics keeps tabs on your design”).

Some products, such as those from Cadence, Mentor Graphics, and Zuken, have tools to get electrical and physical information into the simulation software. When you do your PCB design in these vendors’ tools, the vendors provide a complete representation of the PCB-layer stackup and material, allowing their signal-integrity and fieldsolver tools to use this data in their simulations.

Also make sure that point tools can accept your PCB data. CST and Sigrity take databases from Cadence, Mentor, Zuken, and Altium, and these tools and many others accept ODB (open-database)++ PCB fabrication to define the physical configuration and materials in PCBs. Full-wave-simulation vendors, such as SPEAG and 2Comu, are familiar with 3-D databases and can import STEP (Standard for the Exchange of Product Model Data), IGES (Initial Graphics Exchange Specification), DXF, and other mechanical-solid-modeling outputs. Once in the simulation program, the program meshes the solids with algorithms appropriate to the method.

Defining the mechanical shapes and dielectric constants of the physical design is only part of the EMC-analysis problem. When using a time-domain technique, you can just put the proper time-domain waveforms on the ends of the traces. IBIS (I/O-buffer-information specification), a time-domain look-up table of driver-pin waveforms, can describe the rise and fall of a signal on a pin. You also must define the data on the pin; a PBRS (pseudorandom binary sequence) is often adequate for representing the spectral content of the signal on a functional product.

You can use IBIS-AMI (algorithmic-modeling interface) to define the preemphasis circuits and equalizers in the chips you are using, but it does not define the actual waveforms that will appear when your product is running. Typically, you just use a PBRS into the IBIS-AMI blocks. Meanwhile, your design may have hundreds of traces that might interact.

S-parameters are the best way to represent the spectral content for the sources of EM noise at high frequencies. An S-parameter representation of a PCB block still does not give you the spectral content that the block will output unless you properly excite the block with signals typical of those that the product will use. Using EM simulations for EMC does give rise to a “chicken-or-egg” problem. Sometimes, the only thing that has the adequate representation of the frequency spectrum being radiated is a working board inside a real case. In that situation, it may make no sense to simulate the problem when you can simply test it, but doing simulations is important. You must know where your simulations deviate from actual results, and doing a correlation between the simulations and real measurements allows you to improve your models, your meshing, or your technique. This approach may not save time for the product you are currently working on, but it can shave months or even years off the development of the next one. Getting results from a Spice simulation that creates a near-field model that you then import to a 3-D solver is a good way to stay in control of your EMC problems.

Tools for EM simulation

No single piece of software can do EMC analysis. You should assemble a suite of software tools to help battle your EMC demons. For example, boardlevel tools can ensure that the signals go where you intend instead of radiating to space. All enterprise-class PCB companies have good field-solver tools to help with signal integrity (Reference 3). Mentor Graphics may be most well-known for its HyperLynx tool, but Cadence, Ansoft, and Zuken also have powerful tools that work on a PCB with hundreds or thousands of traces. SiSoft makes a signal-integrity tool similar to HyperLynx. Sigrity Systems offers its software as a point tool to plug into PCB flows. This tool finds how power- integrity problems and signal-integrity problems relate to each other (see sidebar “SI and power integrity are also important”). Once you have a well-designed PCB, you may then have to approach the problem as if you were an RF-board designer.

RF-design-software companies Agilent ADS, AWR Microwave Office, Ansoft, Sonnet, CST, and dozens of others can help you deal with the vagaries of EMC analysis. Most of these companies also offer plug-in software, such as the EMPro software in Agilent’s ADS, which performs EM modeling. These tools also account for metal boxes and shields around the circuits and can evaluate the relationship between the electrical and mechanical aspects of your design—an inherent requirement of RF design. RF designers know that their circuits’ performance changes after the cover is on. RF-design tools can model the cooling slots in the case and tell you the amount of radiation coming from them for a given frequency excitation.

Excitation constituting random fields pouring from your PCB as it operates is a more intractable problem, but field-solver companies CST and Ansoft demonstrate how you can solve it. You use time-domain simulations with real waveforms on multiple traces to do a simulation. You then capture a near-field representation of the radiation from the PCB. At a short distance from a source, the electric and magnetic fields do not directly relate, as they do in a wave propagating through space. You then plug this near-field result into a full-wave solver that can calculate the effects of your product’s case, cables, and other mechanical features.

Software can't think

Field-solver EM simulations do not provide an EMC panacea. Furthermore, they are not magical genies that can solve a design disaster. Field-solver vendors stress that computer simulations are parts of the entire design process, not some tacked-on afterthoughts that you do as a penance when your product fails FCC testing. You can’t expect a computer simulation to identify every area in which you may have to make improvements. However, if you use and understand the simulations of various parts of your design as it progresses, you will be in better shape when submitting your product for FCC and CE testing. In many cases, the most valuable thing that a computer simulation will do is teach you the nonintuitive behavior of EM fields in a complex product. Playing with the configurations, materials, and shielding will help you understand what is going on, and you can design the product to comply with regulations.

With signal frequencies in the gigahertz, a finned heat sink on an FPGA acts as a phased-array antenna, radiating energy in your product. The cooling slots on the case are also phased antennas. Even if you do not have the time or budget to do a full simulation of the electrical signals on the board radiating to a point 3m away, you can still use fullwave simulations. A broadband simulation of the heat sink tells you at which frequencies the sink resonates and the spatial pattern of the resonance. You can also do a broadband excitation of the slotted case. If the frequencies and locations of the heat-sink resonance align with the resonance of the case, those frequencies will cause trouble. The fix may be as simple as rotating the heat sink 90° or changing the spacing of the fins, the slots on the case, or both.

Field-solver programs have steep learning curves, especially for engineers unfamiliar with 3-D simulations. Once you understand the software, you must learn how to import your physical configurations and electrical stimuli. It may seem like an unending task, but once you get a simulation to accurately predict the EMC performance of your product, you will see the attraction of using simulations. They allow you to evaluate things in hours instead of months. They don’t guarantee that your product will pass radiation and immunity tests, but they give you a big head start over companies that simply use “cut-and- try” methods to get their products through FCC and CE approvals. You do testing at the end of the product cycle, when whether you ship the product determines your company’s fortunes.

Smart engineers use software simulations to evaluate EMC in the early phase of the design cycle, moving the risky EMC problems away from the critical product-release phase. They still need to make design and schedule changes but have enough time to efficiently solve the problem without delaying the product’s introduction.

Fuente: http://www.edn.com/article/509651-EM_simulation_for_EMC_keeping_a_lid_on_interference.php
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF

New Antenna From AR Is Approximately 75% Smaller With No Reduction In Key Electrical Performance

July 16, 2010

Souderton, PA -- AR RF/Microwave Instrumentation has unveiled a new antenna that represents another advance in antenna technology.

Model ATR26M6G-1 (26 MHZ – 6 GHz / 5,000 watts) is a wide band, high gain antenna with a proprietary design that combines AR's "bent element" approach with additional innovations. The result is an extremely versatile antenna that provides a size reduction of approximately 75% without sacrificing key electrical performance such as gain and bandwidth. The antenna's size and performance make it uniquely suited for use in both traditional applications and in new compact chambers.

The ATR26M6G-1 features a reduced profile and extremely low VSWR, making it an excellent choice for high-field-strength immunity testing. The size reduction minimizes field loss that can result from "room loading." The broad frequency range addresses existing RF susceptibility requirements as well as anticipated future developments and is matched to work with AR's "W," "S" and "A" Series RF power amplifiers. The robust design can accommodate the high power levels necessary to generate significant E-fields.

The ATR26M6G-1, which is tough and durable enough to withstand the rigors of outdoor use, can also be calibrated for RF emissions testing.

Fuente: http://www.rfglobalnet.com/article.mvc/New-Antenna-From-AR-Is-Approximately-75-Small-0001
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF

New Antenna Technology

Out of sight antennas, Jul 23, 2010

The Yacht Technologies division of Selex Communications, a part of the Finmeccanica group, has announced the launch of their Integrated Antenna Solutions (IAS) to the superyacht market.

Antenna masts are just one aspect of yacht design that are not easy to make aesthetically pleasing to the eye. However, IAS is set to influence the future design of superyachts as the new technology allows for all antenna technology to be concealed within the physical body of the yacht. “Even on the largest superyachts, space for antennas and sensors is limited”, explains John Hodder, Head of SELEX Communications Yacht Technologies. “Both performance and aesthetic considerations influence how and where they can be located. As innovators in superyacht technology, we wanted to bring something to our customers that offers designers the opportunity to create superyachts with clean lines, without limiting performance in any way, IAS offers the ideal solution.”

When asked about this new technology for the industry, James Carley, Senior Designer at Bannenberg & Rowell commented: “It would be great, if they can make it real and make it work.” Carley explains that if a designer were able to shape a single dome so that it worked in harmony with the design of the yacht, it would help the overall look and design of the yacht. The idea of combining all the various satellite and antenna domes into one space would be a great step forward in his opinion, but he is cautious of the idea due to the potential for interference when all the technology is under a single dome.

Selex claims that the IAS overcomes such issues as interference between multiple antennas when transmitting and receiving by combining several antennas, operating on different frequencies, into a single aerial without affecting performance. The new technology will allow for the designing of bespoke antennas for covert installation, such as hiding the antenna in the cowling of the yacht.

“We have considerable experience in IAS across a wide range of platforms”, concludes Hodder. “We have been working closely with designers and shipyards to implement this technology in naval applications for more than a decade, so we can guarantee success.”



Fuente: http://www.superyachtdesign.com/news.asp?newsid=442
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF

Plasma etch and dep tool maker OEM Group adds AlN film foundry services

OEM Group Inc of Gilbert, AZ, USA, which provides equipment to silicon, MEMS, LED, RFID, power device and photovoltaic device makers, has added foundry services to its offerings. Specifically, it is offering high-quality aluminum nitride (AlN) foundry, performed in its applications lab.

Included in the firm’s acquisition in March of the Thin Films and PVD product lines from Tegal Corp of Petaluma, CA, USA, the foundry services use the SFI Endeavor AT PVD (physical vapor deposition) platform to produce piezoelectric AlN films on a variety of 4–6-inch wafers used in surface acoustic wave (SAW), bulk acoustic wave (BAW), FBAR (film bulk acoustic resonator), and micro-electro-mechanical system (MEMS) devices. Equipped with a dual-cathode AC power S-Gun magnetron, the Endeavor AT PVD cluster tool has proven sputter technology that can produce superior film crystallinity, uniformity, and precise stress adjustment, it is claimed.

OEM Group also participates in customer R&D projects by assisting optimization of devices and technology as well as developing deposition processes suited for specific customer requirements.

“Performance of AlN-based electro-acoustic devices such as BAW and FBAR filters, oscillators, and resonating sensors is substantially tied to thin-film technology,” says PVD process development manager Valeriy Felmetsger. “Reactive magnetron sputtering is a method of choice enabling formation of AlN films with a high degree of c-axis texture and thus a strong piezoelectric response. In mass production, the most important criteria of advanced reactive sputtering are process stability and repeatability of the film properties from run to run, and independent control of the film properties such as crystal orientation, thickness, uniformity, and stress.” The SFI Endeavor AT PVD system suits the deposition of film stack, two-step deposition, or deposition of single AlN films, it is added.

“We have widened our breadth of products and services to move beyond tool manufacturing,” says OEM Group president Wayne Jeveli. “Our foundry services are a logical next step given our infrastructure, equipment, and expertise,” he adds. “Our foundry service's success is based on the reliable well developed technology we possess and we know customers can trust; careful analysis by our experts of all technical requirements and precise process adjustments to satisfy these requirements; and our professional reputation based on comprehensive hands-on experience in sputtered films technology.”

Fuente: http://www.semiconductor-today.com/news_items/2010/JULY/OEM_130710.htm

Ver blogger original: http://nubia-anc.blogspot.com/

Materia: CRF

Affinity Biosensors Selects Innovative Micro Technology (IMT) as Foundry Partner for Volume Production of MEMS Particle Mass Sensor

Affinity Biosensors and Innovative Micro Technology, Inc. entered into a strategic foundry partnership today for volume production of suspended mass resonator (SMR) MEMS devices enabling particle measurement in fluidic solutions with femtogram resolution. The SMR MEMS devices are the chips that drive Affinity Biosensors’ ARCHIMEDES Particle Measurement System, which won the Gold Award for the Best New Product at Pittcon 2010, and most recently, the 2010 R&D100 Award, recognizing it as one of the most technologically significant new products of the past year.

Originally conceived at Massachusetts Institute of Technology, IMT refined and developed a robust process for volume production, including a key component to this product – sub-mTorr vacuum, wafer-level packaging (WLP) technology. ARCHIMEDES measures a particle as it traverses through a microfluidic channel embedded in a resonating cantilever. The mass is determined by detecting the change in resonant frequency at the time the particle enters the tip of the cantilever. Achieving femtogram resolution requires the cantilever to have a very high Q-factor that is only accomplished by encapsulating the cantilever in high-vacuum wafer level packaging (WLP).

”Working with IMT has been a very rewarding experience. I know of no other MEMS foundry with the breadth of facilities and depth of expertise needed to develop the sensors for ARCHIMEDES, and to bring them into production. It is not an exaggeration to say that ARCHIMEDES, and perhaps Affinity Biosensors itself, might not exist without our relationship with IMT,” said Dr. Ken Babcock, CEO of Affinity Biosensors.

IMT builds some of the most complex MEMS devices in the market today. Incorporating proven technology modules and platforms, such as WLP, through silicon vias, and 3D microfluidics, help to mitigate program risks and achieve production-friendly processes. As a result, IMT’s customer products are reaching the market in ever faster times.

“Of course, we are always pleased when we can provide a value that enables our customers to achieve true technical differentiation in the market,” stated Dr. John Foster, CEO of IMT. “While the concept of the SMR chip is simple, the technology used to produce these devices is not. We are fortunate to have been able to leverage our standard processes and depth of experience in microfluidics to help shorten the development time of this project and are thrilled to be supporting Affinity Bio in production today.”

About Affinity Biosensors

Affinity Biosensors is pioneering ultra high-resolution mass measurement for real-world applications in industrial manufacturing, research, life sciences, and nanotechnology. Affinity Biosensors introduced ARCHIMEDES as a new gold standard in particle metrology, and is working to extend this capability to mass-based cytometry for biological research, biotechnology, and therapeutics.

About Innovative Micro Technology, Inc.

IMT is a world leader in the production and development of MEMS devices and is the largest pure-play MEMS foundry in the United States. Established in 2000, IMT develops, manufactures, tests, and supplies products to the RF, biotech/biomed, optical communications, infrared, navigation, and general markets, servicing Fortune 500 companies to startups. For more information on IMT and its services, visit the company website at http://www.imtmems.com.

Contacts

Innovative Micro Technology

Theodore Chi, Director of Marketing and Sales

Tel: 1-805-681-2852

ted@imtmems.com

http://www.imtmems.com/

or

Affinity Biosensors

Ken Babcock, CEO

Tel: 805-455-0181

ken@affinitybio.com

http://www.affinitybio.com/

Fuente: http://www.financialpost.com/markets/news/Affinity+Biosensors+Selects+Innovative+Micro+Technology+Foundry+Partner+Volume+Production+MEMS+Particle+Mass+Sensor/3266547/story.html

Ver blogger original: http://nubia-anc.blogspot.com/

Materia: CRF

Fraunhofer ISIT Selects Rudolph Technologies for MEMS Inspection

Rudolph advanced macro inspection system to be used for developing processes for high-volume manufacturing and packaging of inertial MEMS on wafer level.

FLANDERS, N.J., Jul 12, 2010 (BUSINESS WIRE) -- Rudolph Technologies, Inc. /quotes/comstock/15*!rtec/quotes/nls/rtec (RTEC 8.58, +0.46, +5.67%) , a leading provider of process characterization equipment and software for wafer fabs and advanced packaging facilities, announced that the Fraunhofer Institute for Silicon Technology (ISIT) in Germany has placed an order for an NSX(R) Series Macro Inspection System for advanced MEMS processing. The system will be installed this summer in the state-of-the-art 200 mm MEMS pilot production line at ISIT.

"We are pleased to continue working with ISIT on next-generation MEMS processes," said Hartmut Seeger, sales manager for Rudolph in Europe. "ISIT evaluated the NSX System along with several other inspection systems for this application. Acceptance of this tool confirms that the investments we have made to address unique MEMS inspection requirements, including the challenge of wafer handling, are meeting our customers' needs."

The ISO 9001:2008-certified production environment at ISIT enables the development of advanced MEMS devices for inertial, RF and electro-optical applications with the required application-specific packaging technology at the wafer level. The functional integration of extremely small features requires automatic defect inspection at small dimensions with high throughput and limited effect on the wafers. Hermetic wafer level vacuum packaging (with integrated getter) requires an inspection tool that is highly flexible in both hardware and software features.

"Silicon and glass cap wafers are not only fragile, but have deep cavities and sensitive features on both sides of the wafer, requiring a unique wafer handling concept," said Dr. Wolfgang Reinert, team leader-advanced electronic packaging, Fraunhofer ISIT. "The cap wafer inspection results need to be mirrored and interfaced with the ISIT final electrical test equipment for single device traceability and inkless assembly."

Sascha Muhlmann, MEMS engineer, Fraunhofer ISIT, added, "The capabilities of Rudolph's Discover(R) all-surface defect analysis and data management software on the NSX platform support these tasks during the device development phase and after the technology transfer to MEMS pilot production."

The NSX Series is a fast, repeatable macro defect inspection solution used throughout the semiconductor device manufacturing process. Macro defects can be created during wafer manufacturing, probing, bumping, dicing, or by general handling, and can have a major impact on the quality of a microelectronic device. The NSX, specifically designed for back-end manufacturing and often selected by automotive device manufacturers for 100 percent inspection, can handle whole wafers and thinned wafers on film frames. It can quickly and accurately detect yield-inhibiting defects to provide quality assurance and valuable process information.

With this order from Fraunhofer ISIT, the installed base of Rudolph Technologies' NSX Systems totals over 600 worldwide.

The Fraunhofer Institute for Silicon Technology (ISIT) works on design, development and production of microelectronic components as well as micro-sensors, micro-actuators and other components for microsystems technology. Further services offered by the institute are analysis and development of technology pertaining to the quality and reliability of electronic assemblies as well as packaging and mounting technology for microsystems, sensors and multichip modules. www.isit.fraunhofer.de

Rudolph Technologies, Inc. is a worldwide leader in the design, development, manufacture and support of defect inspection, process control metrology, and data analysis systems used by semiconductor device manufacturers worldwide. Rudolph provides a full-fab solution through its families of proprietary products that provide critical yield-enhancing information, enabling microelectronic device manufacturers to drive down costs and time to market. Rudolph offers yield management solutions used in wafer processing and final manufacturing through a family of systems for macro-defect inspection (detection and classification), as well as transparent and opaque thin film measurements.

The company has enhanced the competitiveness of its products in the marketplace by anticipating and addressing many emerging trends driving the semiconductor industry's growth. Rudolph's strategy for continued technological and market leadership includes aggressive research and development of complementary inspection and metrology solutions. Headquartered in Flanders, New Jersey, Rudolph supports its customers with a worldwide sales and service organization. Additional information can be found on the company's web site at www.rudolphtech.com.

Safe Harbor

This press release contains forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995 (the "Act") which include demand for Rudolph's products, Rudolph's existing market position and its ability to maintain and advance such position relative to its competitors and Rudolph's expectations about our future bookings and backlog as well as other matters that are not purely historical data. Rudolph wishes to take advantage of the "safe harbor" provided for by the Act and cautions that actual results may differ materially from those projected as a result of various factors, including risks and uncertainties, many of which are beyond Rudolph's control. Such factors include, but are not limited to, delays in shipping products for technical performance, component supply or other reasons, the company's ability to leverage its resources to improve its positions in its core markets and fluctuations in customer capital spending.

Additional information and considerations regarding the risks faced by Rudolph are available in Rudolph's Form 10-K report for the year ended December 31, 2009 and other filings with the Securities and Exchange Commission. As the forward-looking statements are based on Rudolph's current expectations, the company cannot guarantee any related future results, levels of activity, performance or achievements. Rudolph does not assume any obligation to update the forward-looking information contained in this press release.

Fuente: http://www.marketwatch.com/story/fraunhofer-isit-selects-rudolph-technologies-for-mems-inspection-2010-07-12?reflink=MW_news_stmp
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF

WiSpry Team Wins Smart Antenna Front End (SAFE) Project

The new $8 million SAFE project aims to revolutionize cellular phone antenna technology.

IRVINE, Calif., July 12, 2010 /PRNewswire via COMTEX/ -- On the heels of last week's announcement of its collaboration with IBM, WiSpry, Inc., the leader in tunable radio frequency (RF) semiconductor products for the wireless industry, today announced that it has won, along with key partners, a four year, $48 million DKK ($8 million USD), Smart Antenna Front End (SAFE) project to be funded by Denmark's High Technology Foundation. WiSpry will work together with Aalborg University (AAU), antenna specialist Molex Interconnect, and chipset leader Infineon Technologies to develop tunable antennas and RF front-ends based on WiSpry's tunable RF technology. To work closely with its partners, WiSpry will be establishing a technical presence in Aalborg, Denmark.

The Smart Antenna Front End (SAFE) project's goal is to develop antennas and front-end technology platforms for the next generation of mobile handsets and media devices. SAFE will enable significant reduction in the size and cost of mobile devices while increasing their overall efficiency.

The SAFE project will be led by professor and antenna specialist Gert Frolund Pedersen at Aalborg University's Department of Electrical Systems. Prof. Pedersen stated, "This will be of enormous importance, not only for cell phones, but eventually for all wireless communications."

"Traditionally, RF and antenna development has been separate and this has led to suboptimal solutions. In this program we have, for the first time, brought together expertise from both sides. This consortium has the goal of developing specific control, as well as integration technology for both antenna and RF. This can potentially become a part of all mobile phones in the future," said Per Hartmann Christensen from Infineon Technologies.

Morten Christensen from Molex stated, "During the last 10 years, Molex has built up a unique competency in the antenna area. With the SAFE program we, together with the other parties, have an opportunity to think differently and solve the technical challenges that includes the next generation of smart antennas. I expect this consortium will develop the world's best (smartest) smart antenna systems."

"Inherently agile radio front-ends will provide tomorrow's mobile devices with peak performance at smaller form factors and lower costs," stated Dr. Arthur Morris, chief technology officer, WiSpry. "Wispry's RF tuning and sensing technologies have been developed specifically to provide wide tunability with high precision and easy integration. We expect the SAFE program to prove feasibility of this revolutionary wireless vision and we are excited to join the world-class team in Aalborg."

About WiSpry

Headquartered in Irvine, Calif., WiSpry is a fabless RF semiconductor company that designs and manufactures RF CMOS integrated circuits and components for leading manufacturers of mobile phones, laptops and wireless data communications products. Utilizing the Company's core competency in RF micro-electro-mechanical systems (RF-MEMS) technology, WiSpry creates revolutionary wireless 'System on Chip' MEMS-based RF architectures, and has recently begun shipping products to a Tier 1 mobile handset manufacturer. WiSpry tunable RF-MEMS devices enable the development of tunable RF front-ends, allowing system designers to achieve the architectural innovation required to meet the growing challenges of mobile communications networks. For more information, visit http://www.wispry.com/.

Fuente: http://www.marketwatch.com/story/wispry-team-wins-smart-antenna-front-end-safe-project-2010-07-12?reflink=MW_news_stmp
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF

Design and Development of a Package Using LCP for RF/Microwave MEMS Switches

Morgan Jikang Chen, Member, IEEE, Anh-Vu H. Pham, Senior Member, IEEE, Nicole Andrea Evers, Chris Kapusta, Joseph Iannotti, William Kornrumpf, John J. Maciel, Member, IEEE, and Nafiz Karabudak.

Abstract—We present the development of an ultrahigh moisture-resistant enclosure for RF microelectromechanical system (MEMS) switches using liquid-crystal polymer (LCP). A cavity formed in LCP has been laminated, at low temperature, onto a silicon MEMS switch to create a package. The LCP-cap package has an insertion loss of less than 0.2 dB at X-band. E595 outgas tests demonstrate that the LCP material is suitable for constructing reliable packages without interfering with the operation of the MEMS switch. The package also passes Method 1014, MIL-STD-883 gross leak, and fine leak hermeticity tests. Index Terms—Cavities, chip-on-flex, liquid-crystal polymer (LCP), microelectromechanical system (MEMS), microwave, packaging.

I. INTRODUCTION

PACKAGING is a critical part in bringing the RF microelectromechanical system (MEMS) into application at an affordable cost. MEMS switches are very sensitive to contamination and must be packaged with hermetic or near-hermetic seals in inert noble gas environments. These switches require hermetic packaging to prevent against contaminating particles and moisture. Invasion of particles into the MEMS device can cause the switch to be wedged open, stuck closed where the particle aggravates stiction, or simply degrade performance by acting as a resistive material.

A number of solutions are available for packaging MEMS switches. Several techniques used by industry to package MEMS devices include epoxy seals, glass frit, glass-to-glass anodic bonding, and gold-to-gold bonding. These techniques face two main problems. First, organic materials outgas inside the MEMS cavity during the bonding process due to wetting compounds in the glass, gold, or epoxy layers.

This contamination detrimentally affects the MEMS switch reliability. Second, to achieve a good seal, most bonding processes utilize high temperatures (300 C–400 C) that can degrade MEMS structures. Furthermore, available hermetic packages and ceramic/glass feed-throughs have significant parasitic losses at microwave frequencies, can be expensive, and add significant weight to a system. Packaging MEMS switches into an organic module, in which compact multilayer substrates house active and passive components present even more challenges. Although multilayer chip-on-flex modules using Kapton films are a proven technology for high-density packaging of microwave modules,2 3 Kapton is found to be incompatible with RF MEMS switch packaging due to its high moisture absorption, high out-gassing characteristics, and the need to use high outgassing epoxies for lamination.

In this paper, we present the development of an ultrahigh moisture-resistant package for RF MEMS switches in chip-on-flex modules using liquid-crystal polymer (LCP). We have developed a lamination process to adhere LCP onto silicon to form an enclosure for MEMS. Using multilayer flex and laser-drilled vias, the first level interconnect parasitic losses are negligible at X-band. The microwave measurements demonstrate that the LCP-package has less than 0.2-dB insertion loss and maintains the return loss of a switch to greater than 20 dB. The LCP MEMS package passes the E595 out-gassing test and Method 1014, MIL-STD-883 gross leak, and fine leak hermeticity tests.

Section II provides a brief review of multilayer organic modules, an introduction to LCP, and processes to create the LCP MEMS package. Section III demonstrates the experimental results of peeling strength tests, out-gassing tests, hermeticity tests, and lamination process evaluation. Section IV provides detailed analysis of the electrical performance of a package. Section V demonstrates the electrical performance of a packaged

RF MEMS switch in an LCP enclosure.

II. PACKAGE TOPOLOGY

The multilayer organic multichip module (MCM) is a potential candidate for integrating a system-in-package (SiP) at microwave and millimeter-wave frequencies. This technology has been utilized to package high-peed memory integrated circuits (ICs) and transceiver modules for communications. In 1998, Butler et al. had attempted to use thisMCMtechnology to package MEMS devices. However, the multilayer Kapton is not suitable for hermetic packaging of MEMS. In order to provide hermetic packaging of an RF MEMS switch, we investigate the feasibility of LCP as a multilayer interconnect layer in place of Kapton.

LCP is an emerging low-cost dielectric material that is commercially available as single sheets or laminated substrates that have low moisture absorption (equivalent to glass). Table I compares the basic properties of LCP with Kapton. LCP can be manufactured to have different properties including a coefficient of thermal expansion (CTE) range from (8 -17).10^-6/ K and a glass transition temperature Tg from 280 C to well over 350 C. The use of low and high melting-point temperature LCP allows for layer-to-layer lamination processes without the use of adhesive materials. The main advantages of LCP compared to other organic substrate materials are low moisture absorption, low coefficient of hydroscopic expansion (CHE), excellent barrier properties, and adjustable CTE through thermal treatment processes. Moreover, LCP shows a very low dielectric constant and loss factor, over the frequency range of 1 GHz up to 110 GHz [11]. This unique combination of excellent electrical characteristics, excellent mechanical properties for harsh environment operation, and economical considerations make LCP a serious candidate for all MCM, SiP, and advanced packaging technology.

We have developed a process to laminate LCP onto silicon to form an enclosure for packaging an RF MEMS switch without the use of adhesives. One of the advantages of lamination is the low-temperature processing (below ~315 C), as compared to metallic or glass bonding ( ~400 C). Fig. 1 demonstrates our process flow for laminating LCP on silicon. The process starts with a bare 2-mil-thick LCP that has copper on one side. The copper serves as the roof of the cavity drilled in the LCP film.

 

The MEMS cavity is formed in the 2-mil-thick LCP using laser ablation to the copper lid. The ash is removed using isopropyl alcohol solvent. This cavity acts as a hermetic enclosure formed by the copper lid and LCP walls. The laser ablation is a convenient method to pattern the chemically stable LCP to provide very accurate vertical sidewalls. The single-sided copper-clad LCP film with the laser-drilled cavity is laminated onto an exposed and released silicon switch. The commercially available LCP films have a melting temperature from 240 C to 315 C, which, for robustness of process, is thermally well below any temperature that may impact the MEMS switch. Inert gas can be injected into the cavity to help improve the switch performance during the lamination process. Excellent lamination results have been obtained over a large range of pressures. Through our processing, we obtain 1 m of accuracy using conventional flipchip die bonding equipment.

Once the lamination is completed, square microvias 100- m long along each side and interconnects are formed on the LCP layer. The fabrication of vias and metal interconnects is similar to the process reported in Fig. 2 shows the three-dimensional (3-D) diagram of the LCP packaged RF MEMS switch, and Fig. 3 shows the actual packaged RF MEMS switch prototypes.

III. PROCESS AND PACKAGE EVALUATION

In order to demonstrate that LCP may be used as a package material, tests have been performed to address out-gassing, adhesion strengths, structural integrity, and hermeticity.

A. Out-Gassing Tests

Out-gassing is a major barrier in using polymer materials for packaging RF MEMS. During the processing of polymer in RF MEMS packaging, polymer materials tend to release gas particles that would degrade the reliability of the RF MEMS switch. The ASTM-E 595–93 (1999) tests were employed to evaluate the out-gassing characteristics of LCP materials.

These tests were conducted by measuring mass changes at 125 C under vacuum for 24 h. Results are given as total mass loss (TML), collected volatile condensable materials (CVCMs), and water vapor regain (WVR). TML is the percent difference of mass measured before and after the test. CVCM is the percentage of condensed mass measured on a collector plate over the initial specimen mass. WVR is calculated by placing the measured specimens through 50% relative humidity at 23 C for 24 h, and the value is given as the percentage of increase of specimen mass before and after humidity conditioning.

Historically, a TML of 1% and a CVCM of 0.1% are the maximum levels for materials used in spacecraft applications. As seen from Table II, the experimental results demonstrate that the LCP has passed the out-gassing tests and satisfies the requirements for spacecraft applications. More importantly, even though LCP is a polymer material, it has negligible out-gassing and is suitable for RF MEMS switch packaging.

B. Adhesion and Package Integrity

One of the advantages of LCP films is that they are able to adhere to other materials without the use of external adhesives in a lamination process. This feature not only simplifies the packaging process, but also reduces the electrical loss that is associated with lossy adhesive materials. Out of reliability concerns, adequate adhesion strengths are required because either a weak LCP-to-silicon or a weak LCP-to-metal bond could prevent vias from being formed and contacted correctly.

We have conducted a pulling test to evaluate the adhesion strength of LCP on silicon using a Chatillon pull tester. Fig. 4 shows a cross section of the test structure and how the experiment has been conducted. The experimental results demonstrate that the adhesion of LCP onto Si is more than 3 lbs/in. A comparison of sputter adhesion strengths is provided in Fig. 5, which indicates that the 3-lbs/in adhesion strength is adequate to provide a reliable enclosure. A photograph of a test sample after being subjected to a peel test is shown in Fig. 6. It is interesting to note that even though the Cu/LCP was being separated from Si, it was actually the Cu/LCP interface that came apart first, which attests to the high lamination strength between LCP and silicon.

C. Structural Integrity

From the peel testing, we discovered that optimal lamination strength actually occurred over a temperature range around the melting temperature ( ), as opposed to simply being above a certain threshold value. If the lamination temperature was too low, the lamination strength would be poor. Conversely, if the lamination temperature was too high, then widely varying nonuniform lamination strengths occurred along the interface of LCP and silicon. At the extremes, nonuniform lamination at the interface gave the appearance of good bonds speckled in regions of generally poor lamination. Under optimal conditions, our peel tests show LCP-to-silicon lamination to be in excess of 10 lbs/in.

Fig. 7(a) shows an open rectangular hole in LCP laminated on a silicon substrate that has interdigitated fingers. This rectangular hole is the same size as the cavity used in the MEMS switch enclosure. Fig. 7(b) shows the cross section of the laminated LCP onto Si. As can be seen from Fig. 7(a), after the lamination, the LCP has reflowed and altered the original shape of the sharp rectangular hole. The width of the rectangular hole is 200 m. The reflow is measured to be less than 5 m at the midpoint of the cavity sidewall and 25 m at the corners (noncritical features).

D. Hermeticity Tests

It is well known that polymer materials are usually unsuitable for hermetic packaging because of their high permeabilities, which cause failure during fine leak testing. In order to establish that LCP would be viable for hermetic enclosures, hand calculations are performed based on referred data. LCP has been reported to have a permeability of 2.19 10 cm s for helium in LCP. This value may be compared to the hermetic shielding material Corning 7740 glass in helium, which has a leak rate of 8.5 10 cm s. Package hermeticity is quantitatively analyzed by using the diffusion leak rate closed-form approximation equation Leak rate (1) where is the permeability, is the exposed package area, is the pressure difference, and is the package wall thickness.

Using a permeability of 2.19 10 cm s for helium in LCP, an exposed area of 0.22 mm , an effective wall thickness of 300 m, and pressure as specified for testing the package with 7.5 10 mm cavity volume, the leak rate is estimated to be 6.424 10 atm cm s. This value is significantly below the cutoff condition required by Method 1014, MIL-STD-883.

Gross and fine leak hermetic testing has been performed on five LCP-packaged MEMS switches at Six Sigma.4 These parts are fully functional with both dc and RF via connections. The gross and fine leak tests evaluate the hermetic properties of the LCP packages in accordance with Method 1014, MIL-STD-883. Gross leak is generally indicative of structural failure, while fine leak more generally detects contamination pathways by bulk diffusion mechanisms through materials. Gross-leak testing is performed under 60 pounds per square inch guage relative to atmosphere (PSIG) of perfluorocarbon fluid for 125 min and immediately vacuumed under 5 torr for 30 s. The parts are then submerged in a bubble tester and visually inspected for leaks, as indicated by the appearance of any bubbles from the parts. Fine leak testing is performed under 125 min, 60 PSIG helium soak, followed by a 5-torr vacuum for 1 min. The experimental results demonstrate that our packages have passed the gross and fine leak tests in accordance with Method 1014, MIL-STD-883. Due to the small volume size of our package ( 0.06 mm ), standard detection methods may not be capable of measuring the species inside the cavity. Hence, it is questionable if Method 1014, MIL-STD-883, which is the current standard test, can provide conclusive results on hermeticity for small-volume packages.

IV. ELECTRICAL PACKAGE DESIGN AND SIMULATIONS

In order to evaluate the effects of the package on RF MEMS switches, full-wave electromagnetic simulations have been conducted using Ansoft High Frequency Structure Simulator (HFSS) software that employs a finite-element method. The basic structure for studying insertion loss and return loss includes a bare microstrip transmission line on silicon with a bulk conductivity S m. This structure is considered as an unpackaged device, shown in Fig. 8(a). The bare microstrip line is then packaged in LCP ( , ) with a 2-mil height cavity capped by a copper lid, as shown in Fig. 8(b). Copper vias 100 m by 100 m with 5- m-thick walls form the first-level interconnect. Each metal layer is also 5- m thick.

The chip is 3000 m by 3000 m. Agilent’s Advanced Design System (ADS) LineCalc, which uses close-form equations for calculating impedance and transmission-line geometry, is employed to determine the width of microstrip lines on 254- m-thick Si. The widths of 50- and 80-microstrip lines (unpackaged) are found to be 197 and 50.7 m, respectively. In the packaged simulation, the microstrip section feeding to the coplanar waveguide is deembedded at the port.

Fig. 9 shows the simulation results of the unpackaged and packaged microstrip lines. When the 80- microstrip line is packaged with a 2-mil-high metal lid, the characteristic impedance is tuned down closer to 50 . In this case, the return and insertion losses of the packaged 80- microstrip lines improves from 13 to 25 dB and from 0.76 to 0.42 dB, respectively, at 10 GHz. The insertion and return losses of the 50- microstrip line worsens from 0.581 dB unpackaged to 0.624 dB packaged and from 24.1 dB unpackaged to 20.6 dB packaged, respectively at 10 GHz.

Table III compares simulation results of unpackaged and packaged 50- and 80- microstrip lines in 1- and 2–mil-high metal lids. High characteristic impedance microstrip lines are tuned closer to 50- transmission lines when they become striplines with 1- and 2-mil high metal lids. The capacitance per unit length of the striplines increases, which, in turn, decreases the characteristic impedance. This phenomena is described by the well-known equation for characteristic impedance.

In our research, the MEMS switch has been designed to have a high characteristic impedance ( 80 ) without a package. Hence, we expect that the package will improve the matching of the device to a 50- system. For mechanical robustness, we have chosen a 2-mil-high cavity. An equivalent-circuit model for the microvia interconnect has been developed from simulations using the Sonnet Software that employs the method of moments. This model targets the -band to understand the switch performance. The interconnect model is shown in Fig. 10 to have fF, pH, and models the capacitance between the via to the surrounding ground, and models the inductance associated with the narrow via constructed through the LCP thin film from the outer package to the metal trace on chip-parameters are measured from a packaged thru line.

An analytical method (ADS) is used to deembed all elements in the path other than the interconnect using the technique shown in. Fig. 11 compares modeled and measured -parameters of the transition. This is an agreement to 0.02 dB between model and measurement insertion losses at 10 GHz, which is our frequency of interest. Model and measurement both show less than 0.07-dB insertion loss per package transition at 10 GHz. Return loss shows agreement to less than 4-dB difference between modeled and extracted measurement. This lumped circuit strictly models the via interconnect. When devices are packaged, the interconnects and the additional copper over the packaged device together can cause tuning effects.

V. MEASURED RESULTS

S-parameter measurements have been performed with a Cascade probe station, an Agilent PNA E8364B network analyzer, and Picoprobe coplanar-waveguide probes. A load-reflect-match (LRM) calibration was performed to establish the reference planes to be at the RF probe tips. A dc probe is used to electrostatically bias the switch on with 90 V. The measured results of the LCP packaged switch in the closed state for insertion loss are provided in Fig. 12 over the -band region and plotted up to 18 GHz. Our packaged switches show a total insertion loss of 0.45 dB at -band due to the low-loss LCP material, microvias, and excellent shielding. This includes the additional 0.07 dB loss per interconnection at the input and output with 0.3 dB being attributed to the MEMS switch at -band. In addition, the measured return loss is better than 25 dB. The metal cap of the package tunes the characteristic impedance of the switch closer to 50 . Hence, the return loss of the packaged switch is improved to less than 25-dB return loss.

The -parameters of the packaged MEMS switch had also been measured in the open or off states (0 V \#\bias). Fig. 13 shows the measured -parameters of the off-state switch. The measured isolation of the packaged switch is 15 dB, which remains relatively the same as the unpackaged switch to within 1 dB.

Since the particular switches we use had been optimized for an 80- characteristic impedance system, rather than a 50- system, the isolation is a better metric of the packaging.

VI. CONCLUSION

This paper has successfully demonstrated an ultrahigh moisture-resistant RF MEMS switch enclosure using LCP. Simulations show that the entire package introduces miniscule electrical degradation to the overall circuit performance. Insertion loss of the LCP packaged switch is roughly 0.5 dB at -band with return loss greater than 25 dB and isolation loss of 14 dB.

ACKNOWLEDGMENT

The authors wish to acknowledge the collaborative work between the Microwave Microsystems Laboratory, University of California at Davis, the General Electric Global Research Center, Niskayuna, NY, Radant MEMS Inc., Stow, MA, and Lockheed Martin Commercial Space Systems, Newtown, PA.

Fuente: http://www.ece.ucdavis.edu/mml/papers/J11.pdf
Ver blogger original: http://nubia-anc.blogspot.com/
Materia: CRF